The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We introduce for the first time a novel integration scheme of CBRAM cells, where the Cu electrode is patterned using a subtractive dry-etching process. We demonstrate excellent performances of 30nm-size cells (1µs-write at ≤50µA, >106 endurance, excellent retention at 150°C) as well as scaling potential of CBRAM down to 10nm-node using 5nm-thick Cu electrodes.
We present a novel selector made of doped-chalcogenide material. This selector not only achieves low holding voltage (0.2 V) and large on/off ratio (>107), but also exhibits the high on-current density (>1.6 MA/cm2) and large hysteresis window (1.2 V). Besides, excellent selector performances with ultra-low off-state leakage current (10 pA), high switching speed (<10 ns), high endurance (>10...
We report on the first demonstration of the CMOS-compatible integration of high-quality InGaAs on insulator (InGaAs-OI) on Si substrates by a novel concept named Confined Epitaxial Lateral Overgrowth (CELO). This method, based on selective epitaxy, only requires the use of standard large-area silicon substrates and typical CMOS processes. It enables the fabrication of InGaAs-OI starting from both...
Extremely scaled high-k gate dielectrics with high quality electrical interfaces with arsenide (As) and antimonide (Sb) channels are used to demonstrate complimentary ‘all III–V’ Heterojunction Vertical Tunnel FET (HVTFET) with record performance at |VDS|=0.5V. The p-type TFET (PTFET) has ION =30µA/µm and ION/IOFF =105, whereas the n-type TFET (NTFET) has ION =275µA/µm and ION/IOFF=3×105, respectively...
Robotics has been expected to realize innovation by the cost reduction of manufacturing and service delivery for employers, the burden reduction of labors for employees, and the quality upgrade of products and services for their customers. This talk introduces recent trends of robotics for the innovation mainly taking place in Japan. The robots for the cost reduction include industrial robots and...
This work presents experimental demonstration of InAs single and dual quantum well (DQW) heterostructure FinFETs (FF) and their superior performance over In0.7Ga0.3As QW FF. Peak mobility of 3,531 cm2/V-sec and 3,950 cm2/V-sec are obtained for InAs single QW FF and InAs DQW FF, respectively, at a fin width (Wfin) of 40nm and LG = 2µm. Peak gm of 480 µS/µm, 541 µS/um; IDSAT of 121 µA/µm, 135 µA/µm;...
A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um2 HDC SRAM cells are the most aggressive design rules reported for 14/16 nm node SoC process to achieve Moore's Law 2x density scaling over 22 nm node. High performance NMOS/PMOS...
FinFET has become the mainstream logic device architecture in recent technology nodes due to its superior electrostatic and leakage control [1,2,3,4]. However, parasitic capacitance has been a key performance detractor in 3D FinFETs. In this work, a novel low temperature ALD-based SiBCN material has been identified, with an optimized spacer RIE process developed to preserve the low-k value and provide...
We report a comprehensive evaluation of different device architectures from a device and circuit performance viewpoint: gate-all-around (GAA) nanowire (NW) FETs vs. triple-gate finFETs, both built using various doping schemes. GAA devices are obtained via a fins release process, high density compatible, at replacement metal gate (RMG) module, and outperform others per footprint. Junctionless (JL)...
We have demonstrated high performance operation of planar-type tunnel field-effect transistors (TFETs) using Ge/ III–V materials. Tensile strain in Si channels combined with the Ge source can enhance the tunneling current because of the reduced effective bandgap. The fabricated Ge/sSOI (1.1 %) TFETs show high Ion/Ioff ratio over 107 and steep minimum subthreshold slope (SS) of 28 mV/dec. It is found...
For the first time, we demonstrate that A-G model extracted from short Vg-accelerated stresses can predict both long term DC and AC NBTI under low and dynamic operation Vg. This is achieved by successfully separating non-saturating defects from the saturating ones, allowing reliable extraction of power exponents needed for long term prediction. Unlike R-D model, A-G model does not require solving...
This paper reports a novel material/process-based design for reliability-aware Ge gate stack for the first time. Initially good characteristics of Ge gate stacks do not necessarily guarantee the long-term device reliability. To overcome the big hurdle, we have investigated the stability of GeO2 network as well as the formation of new high-k. The very robust Ge gate stack with both 0.5 nm EOT and sufficiently...
A new phase change material that provides fast SET speed, high cycling endurance, and large resistance window suitable for MLC SCM is investigated. Thorough understanding of the factors that affect the resistance distribution taught us to avoid operating near the melting temperature of the phase change material. By exploiting the self-converging property of low current SET operation we have designed...
For the first time, we present a Phase Change Memory (PCM) device with an optimized Ge-rich GeSbTe (GST) alloy integrated on a 12Mb test vehicle. We confirm that PCM can guarantee high data retention in extended temperature range and we provide the understanding of the high thermal stability of the two programmed states. We show how the elemental distribution reaches an equilibrium at the core of...
Multi-level-cell (MLC) is a critical technology to achieve low bit cost for phase change memory. However, resistance drift is an intrinsic material property that kills memory window and imposes formidable challenges for MLC. In this work, we report a radically different sensing concept that exploits the non-linear R-V characteristics of PCM that can easily accommodate 8 resistance levels in three...
We demonstrated that reduced graphene oxide (rGO) can suppress electromigration (EM) of Cu interconnect lines. This improvement in the EM lifetime is attributed to the presence of functional groups between the rGO and Cu atoms. Further enhancement of the EM lifetime was achieved by increasing the functionality of graphene by mixing graphene oxide (GO) with polyvinylpyrrolidone (PVP). It is revealed...
A high-programming-throughput three-dimensional (3D) vertical chain-cell-type phase-change memory (VCCPCM) array for a next-generation storage device was fabricated. To increase the number of write cells at one time by reducing resistance of bit and source lines, the VCCPCM array includes plate electrodes and double-gate vertical-chain-selection MOSs with 5-nm-thick poly-Si channels. In addition,...
A 50nm topological-switching random-access memory (TRAM) was fabricated for the first time. A high-quality GexTe1−x/Sb2Te3 superlattice film enabled set and reset voltages of TRAM to be less than 40% of those of PRAM. Statistical analysis of 16kb data showed the reset voltage to be less than 1.2 V, the lowest as a TRAM test chip.
Strained Ge p-channel FinFETs on Strain Relaxed SiGe are integrated for the first time on high density 45nm Fin pitch using a replacement channel approach on Si substrate. In comparison to our previous work on isolated sGe FinFETs [1], 14/16nm technology node compatible modules such as replacement metal gate and germanide-free local interconnect were implemented. The ION/IOFF benchmark shows the high...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.